March 2023
A research paper from out is accepted for publication in Elsevier’s Journal on Microprocessors and Microsystems – title of the paper is “FM-ModComp: Feature Map Modification and Hardware-Software Co-Comparison for Secure Hardware Accelerator-based CNN Inference ” by T. A. Odetola, A. Adeyemo, F. Khalid, and S. R. Hasan.
February 2023
A research Paper from our group – is published IEEE Access – titled as ” StAIn: Stealthy Avenues of Attacks on Horizontally Collaborated Convolutional Neural Network Inference and Their Mitigation”, By A. Adeyemo, J. Sanderson, T. A. Odetola, F. Khalid, S. R. Hasan
August 2022
My Student Tolulope A. Odetola successfully defended his PhD thesis titled “Hardware Verification and Security Challenges in Distributed Convolutional Neural Network Inference”, in the ECE Department of Tennessee Tech University. Tolulope is working as Senior Machine Learning Software Engineer for Whirlpool Inc.
Congratulations Tolu !!!
June 2022
T. Odetola presented our paper titled “Hardening Hardware Accelerator Based CNN Inference Phase against Adversarial Noises” in Work in Progress session of IEEE International Symposium of Hardware Oriented Security and Trust (HOST)
May 2022
My Student Travis Sandefur successfully defended his MSc thesis titled “Towards Real-Time Intelligent Computer Vision on Xilinx FPGAs: Exploring High-Level Synthesis and Peta-Linux Environments”, in the ECE Department of Tennessee Tech University
Congratulations Travis !!!
April 2022
Two papers from our research group were accepted for publication in International Symposium on Circuits and Systems (ISCAS-2022) —
- T. Sandefur, S. R. Hasan “Framework to Benchmark CNNs (FaBCNN) for Processing Real-Time HD Video Streams on FPGAs”, in IEEE International Symposium on Circuits and Systems–ISCAS’22.
- A. Adeyemo, T. A. Odetola, S. R. Hasan “Towards Enabling Dynamic Convolution Neural Network Inference for Edge Intelligence”, in IEEE International Symposium on Circuits and Systems–ISCAS’22.
August 2021
My PhD student Tolulope Odetola presented our group’s papers in International IEEE MidWest Symposium on Circuits and Systems (MWSCAS’21) – the titled of the papers are:
- Dynamic Distribution of Edge Intelligence at the Node Level for Internet of Things
- Security Analysis of Capsule Network Inference Using Horizontal Collaboration
- ORDA: A Winograd Offline-Runtime Decomposition Algorithm for Faster CNN Inference
July 2021
Our NSF Funded REU 2021 Site is successfully Concluded
Hawzhin Mohamed , successfully defended his PhD thesis titled “Haredare Attacks on IoT Based Network: A Secure Edge Intelligence Perspective”, Dr. Hawzhin Mohamed has joined Penn State at Altona as an Assistant Professor
Congratulations Hawzhin !!!
May 2021
We Welcome our NSF funded REU students to our College of Engineering
My PhD student Tolulope Odetola presented our group’s paper in International Symposium on Circuits and Systems (ISCAS’21) his paper on “SoWaF: Shuffling of Weights and Feature Maps: A Novel Hardware Intrinsic Attack (HIA) on Convolutional Neural Network (CNN)”
September 2020
My international collaborator F. Khalid prsented our paper in Embedded Systems Week – This paper is accepted for publication in IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems. The title of the paper is “MacLeR: Machine Learning-based Run-Time Hardware Trojan Detection in Resource Constrained IoT Edge Devices”
August 2020
My PhD student Tolulope Odetola presented our group’s paper in 63rd International IEEE MidWest Symposium of Circuits and Systems. The titles are
1.An Edge Intelligence Framework for Resource Constrained Community Area Network
2. Deployment of Object Detection Enhance with Multi-lable Multi-Classificagtion on Edge Devices
May 2020
Our paper (with my international collaborators) got accepted in Elseviers’ Microprocessors and Microsystems Journal-
F. Khalid*, S. R. Hasan, S. Zia, O. Hasan, F. Awwad, M. Shafique, “MacLeR: Machine Learning-based Run-Time Hardware Trojan Detection in Resource Constrained IoT Edge Devices”, IEEE Transaction on Computer-Aided Design of Integrated Circuis and Systems, 2020 (Early access: 10.1109/TCAD.2020.3012236)
May 2020
Ogheneuriri (Riri) Oderhohwo successfully defended her MS thesis titled “Multi-Label Multi-Classification Method with Objecte Detection Implementation for Edge Intelligence”
Congratulations Riri !! – She will start working for Intel Inc. February 2020
One of our papers, with my student Mohamed Hawzhin , got accepted in IEEE Access. The title of the paper is: “FusIon- On-Field Security and Privacy Preservation for IoT Edge Deices: Concurrent Defense Agains Multiple Types of Hardware Trojan Attacks” – DOI: 10.1109/ACCESS.2020.2975016
December 2019
Katie Grooves has successfully defended her MS thesis titled “A Complete Methodology for Implementing Deep Learning Architecture on PYNQ-Z1; Leveraging Pipeline and Distributed Network”
Congratulations Katie !!
June 2019:
NSF has renewed our REU Site. REU Site has commenced from 6/3/2019 for 10 weeks
May 2019:
Muluken Hailesellasie successfully defended his PhD thesis titled as
“Hardware Architecture Design for Regular Convolutional Neural Networks Targeting Resource-Constrained Device with an Automated Framework”
Congratulations Muluken !!
Muluken will start working for Intel Corporation
March 2019:
One of our papers, with my student Muluken. T. Hailesellasie, got accepted in IEEE Access. The title of the paper is: “MulNet: A Flexible CNN Processor with Higher Resource Utilization Efficiency for Constrained Devices”
February 2019:
One of our papers, with my student Enahoro Oriero, got accepted in Integration, The VLSI Journal. The title of the paper is: “Survey on Recent Counterfeit IC Detection Techniques and Future Research Directions”
January 2019:
One of our papers, with my student Muluken. T. Hailesellasie, got accepted in IEEE International Symposium on Circuits and Systems (ISCAS – 2019)
Congratulations Muluken !!!
December 2018:
Our REU Site is renewed for another 3 years: “Secure and Privacy-Preserving Cyber-Physical Systems: Software and Hardware Approaches” We are currently accepting applications for 201 summer session. for more details please visit : http://www.cae.tntech.edu/~mmahmoud/REU/REU.htm
August 2018:
1) REU Students site reached its successful conclusion
2)I presented two of our papers with my students, H. Mohammed, E. Oriero, and J. Howell, in the IEEE International MidWest Symposium of Circuits and Systems
May 2018:
My international collaborator F. Khalid prsented our paper with my PhD sutdent, Muluken. T. Hailesellasie, in International Symposium on Circuits and Systems (ISCAS). The title of the paper is “FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements”
June 2017:
Three of my papers got accepted in IEEE International MidWest Symposium on Circuits and Systems (MWSCAS – 2017). One paper is with my MS student Oluwadara Adegbite.
Congratulations Dara !!!
May 2017:
1. Muluken. T. Hailesellasie presented his paper in International Symposium on Circuits and Systems (ISCAS). The title of the paper is “A Fast FPGA-Based Deep Convolutional Neural Network using Pseudo Parallel Memories”
April 2017:
Oluwadara Adegbite successfully defended his M.S. thesis titled as
“A Novel and Cost-Effective Test Bed Implementation of Side Channel Attacks on Advanced Encryption Standard (AES): Leveraging Correlation Power Analysis and Machine Learning”
Congratulations Dara !!
Dara has joined Intel Corporation
March 2017:
1. Our journal paper got accepted for publication in Integration, The VLSI Journal (with my recently graduated student, Dr. S. F. Mossa)
Congratulations Siraj !!!
S. F. Mossa, S. R. Hasan, O. S. A. Elkeelany, “Hardware Trojans in 3-D ICs Due to NBTI Effects and Countermeasure”, Integration, The VLSI Journal (accepted for publication)- 2017
2. Two of my papers got accepted in International Symposium on Circuits and Systems (ISCAS – 2017). One paper is with my PhD graduate student Muluken. T. Hailesellasie. (acceptance rate ~ 45%)
Congratulations Muluken !!!
February 2017:
Our REU student, Sam Kottler’s work is accepted for publication in IEEE SouthEast Conference
Congratulations Sam !!!
S. Kottler, M. Khayamy, S. R. Hasan, O. Elkeelany, “Formal Verification of Ladder Logic programs using NuSMV”, accepted for publication in IEEE SouthEast Conference, 2017
January 2017:
A journal paper is accepted for publication (with my graduate student, Siraj F. Mossa) in Integration , The VLSI Journal:
Congratulations Siraj !!!
S. F. Mossa, S. R. Hasan, O. Elkeelany, “Self-triggering Hardware Trojan: Due to NBTI Related Aging in 3-D ICs”, Integration, The VLSI Journal (in press) – 2017
November 2016:
Our paper (with my international collaborators) got accepted in IEEE/ACM conference on Design Automation Test Europe (DATE) acceptance rate (~35%):
F. K. Lodhi, S. R. Hasan, O. Hasan, F. Awwad, “Power Profiling of Microcontroller’s Instruction Set for Runtime Hardware Trojans Detection without Golden Circuit Models”, accepted for publication in IEEE/ACM Conference on Design Automation and Test Europe (DATE), Lausanne, Switzerland, 2017
October 2016:
Our paper, in collaboration with Air Force Research Lab (AFRL), got accepted in IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST):
S. R. Hasan, Charles Kamhoua, Kevin Kwiat and Laurent Njilla, “Translating Circuit Behavior Manifestations of Hardware Trojans using Model Checkers into Run-time Trojan Detection Monitors” accepted for publication in AsianHOST, Taipei, Taiwan, 2016
September -2016:
Published a journal paper in Journal of Electronics Testing:
F. K. Lodhi, S. R. Hasan, O. Hasan, F. Awwad, “Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification”, Journal of Electronics Testing Theory and Applications (JETTA), 2016, (in press)
August – 2016:
1) Dr. Siraj F. Mossa, successfully defended his thesis titled as
“Investigation of Reliability and Security Issues in Through Silicon Via Based Three-Dimensional Integrated Circuits”
Dr. Mossa is now working in Intel Corporation
2) REU Students site reached its successful conclusion
July- 2016:
1) Dr. Hasan is awarded with Summer Faculty Fellowship in Air Force Research Lab (AFRL) in Rome, NY
2)Oral Presentation at Air Force Research Lab, Rome, NY, on ” Towards Run-Time Hardware Trojan Detection Using Circuit Behavior Profiling: Leveraging Game Theory and Formal Verification”, July, 2016
June- 2016:
1) First batch of REU students commenced their work at our REU site
2) My graduate student O. Adegbite presented a poster in IEEE/ACM Design Automation Conference (DAC) (acceptance rate ~ 33%):
O. Adegbite, S. R. Hasan, “Correlation Power Analysis Attack on PIC Based AES 128 Implementation without Triggering Signal: Leveraging Elastic Alignment”, (extended abstract) in Design Automation Conference (DAC), 2016, Austin, TX
May- 2016:
1) Published papers in ISCAS-2016:
- W. Gul, S. R. Hasan, O. Hasan, F. K. Lodhi, F. Awwad, “Synchronously Triggered GALS Design Templates Leveraging QDI Asynchronous Interface”, in IEEE international symposium of circuits and systems (ISCAS’ 2016)
- F. K. Lodhi, I. Abbasi , F. Khalid , O. Hasan, F. Awwad and S. R. Hasan, “A Self-learning Framework to Detect the Intruded Integrated Circuit”, in IEEE international symposium of circuits and systems (ISCAS’ 2016)
2) Invited talk at National University of Science and Technology, Islamabad, Pakistan, on “Digital Hardware Design Security”, May, 2016
April- 2016
Two of my graduate students, O. Adegbite and M. Hailesellasie, from the group got internship in Intel Corporation
January- 2016
Funding
| NSF Research Experience for Undergraduates (REU) | Secure and Privacy Preserving Cyber Physical Systems (2016- 2019), We are currently accepting applications for 2016 summer session. for more details please visit : http://www.cae.tntech.edu/~mmahmoud/REU/REU.htm |
ICT-Funds (UAE Govt. ) | Investigation of Effective Management of Energy Demand in Distribution Management Systems of Smart Grids using Formal Verification Methods (More details to follow, stay tuned) |
Graduate Students
Ph.D Student Siraj Fulum Mossa published a journal paper in IET Circuits, Devices and Systems. The title of the paper is “Grouped through silicon vias (TSV) for lower Ldi/dt drop in three-dimensional integrated circuits (3-D IC), January 2016.
Following is the link: http://digital-library.theiet.org/content/journals/10.1049/iet-cds.2015.0065
In an international collaboration we published a journal paper in Integration, the VLSI Journal titled as “Clock Domain Crossing (CDC) in 3D-SICs: Semi QDI Asynchronous vs Loosely Synchronous”. Following is the link:
http://www.sciencedirect.com/science/article/pii/S0167926015000541