My Publications

Refereed Journal Articles:

  1. A. A. Adeyemo, J. J. Sanderson, T. A. Odetola, F. Khalid and S. R. Hasan, “StAIn: Stealthy Avenues of Attacks on Horizontally Collaborated Convolutional Neural Network Inference and Their Mitigation,” in IEEE Access, vol. 11, pp. 10520-10534, 2023, doi: 10.1109/ACCESS.2023.3241096.
  2. Tolulope A. Odetola, Adewale Adeyemo, Faiq Khalid, and Syed Rafay Hasan, “FM-ModComp: Feature Map Modification and Hardware-Software Co-Comparison for Secure Hardware Accelerator-based CNN Inference”, Elsevier’s Microprocessors and Microsystems (in press).
  3. Si, Haijun, Zhicheng Zhang, Orkhan Huseynov, Ismail Fidan, Syed Rafay Hasan, and Mohamed Mahmoud. 2023. “Machine Learning-Based Investigation of the 3D Printer Cooling Effect on Print Quality in Fused Filament Fabrication: A Cybersecurity Perspective” Inventions 8, no. 1: 24. https://doi.org/10.3390/inventions8010024
  4. T. Odetola, K. Groves, Y. Mohammed, F. Khalid, S. R. Hasan, “2L-3W: 2-Level 3-Way Hardware-Software Co-Verification for the Mapping of Convolutional Neural Network (CNN) onto FPGA Boards”, Springer Nature Journal of Computer Science, January 2022.
  5. T. Odetola, F. Khalid, T. Sandefur, H. Mohammed, and S. R. Hasan, “FeSHI: Feature Map Based Stealthy Hardware Intrinsic Attack”, IEEE Access, 2021 (in press) DOI: 10.1109/ACCESS.2021.3104520
  6. F. Khalid, S. R. Hasan, S. Zia, O. Hasan, F. Awwad, M. Shafique, “MacLeR: Machine Learning-based Run-Time Hardware Trojan Detection in Resource Constrained IoT Edge Devices”, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol. 39, Issue 11, 11/2020; DOI: 10.1109/TCAD.2020.3012236
  7. F. Khalid, S. R. Hasan, O. Hasan, M. Shafique “SIMCom: Statistical Sniffing of Inter-Module Communications for Runtime Hardware Trojan Detection” Elsevier’s Microprocessors and Microsystems Journal, September 2020 – https://doi.org/10.1016/j.micpro.2020.103122
  8. W. Ahmad, O. Hasan, F. Awwad, N. Bastaki, S. R. Hasan, ” Formal Reliability Analysis of an Integrated Power Generation System Using Theorem Proving”, IEEE Systems Journal, 2020 (in press) – DOI: 10.1109/JSYST.2020.2970107
  9. H. Mohammed, S. R. Hassan, F. Awwad, “FusIon: On-Field Security and Privacy Preservation for IoT Edge Devices: Concurrent Defense Against Multiple types of Hardware Trojan Attacks” IEEE Access, 2020  DOI: 10.1109/ACCESS.2020.2975016
  10. M. T. Hailesellasie, S. R. Hasan, “MulNet: A Flexible CNN Processor with Higher Resource Utilization Efficiency for Constrained Devices”  IEEE Access, Vol. 7, pp. 47509-47524, December 2019, 10.1109/ACCESS.2019.2907865
  11. E. Oriero, S. R. Hasan, “Survey on Recent Counterfeit IC Detection Techniques and Future Research Directions” Integration, The VLSI Journal, Vol. 66, pp. 135 – 152, May 2019, https://doi.org/10.1016/j.vlsi.2019.02.006
  12. A. Ahmed, O. Hasan, F. Awwad, N. Bastaki, S. R. Hasan, “Formal Asymptotic Analysis of Online Scheduling Algorithm for Plug-in Electric Vehicles’ Charging” Energies 12, no. 1 (2019): 19 https://doi.org/10.3390/en12010019
  13. F. K. Lodhi, S. R. Hasan, O. Hasan, F. Awwad, “Runtime Hardware Trojan Monitors Though Modeling Burst Mode Communication using Formal Verification”, Integration, The VLSI Journal, Vol. 61, pp. 62-76, March 2018, https://doi.org/10.1016/j.vlsi.2017.11.003
  14. M. T. Hailesellasie, S. R. Hasan, “Intrusion Detection in PLC Based Industrial Controls Systems Using Formal Model of the System in Conjunction with Graphs”, Journal of Hardware and Systems Security, Vol. 2, Issue 1,  pp. 1-14, March, 2018 https://link.springer.com/article/10.1007/s41635-017-0017-y)
  15. S. F. Mossa, S. R. Hasan, O. S. A. Elkeelany, “Hardware Trojans in 3-D ICs Due to NBTI Effects and Countermeasure”, Integration, the VLSI Journal, Vol. 59, pp. 64 – 74, September, 2017. DOI: http://dx.doi.org/10.1016/j.vlsi.2017.03.009
  16. S. F. Mossa, S. R. Hasan, O. S. A. Elkeelany, “Self-triggering Hardware Trojan: Due to NBTI Related Aging in 3-D ICs”, Integration, The VLSI Journal, Vol. 58, pp. 116 – 124, June, 2017  DOI:  http://dx.doi.org/10.1016/j.vlsi.2016.12.013
  17. F. K. Lodhi, S. R. Hasan, O. Hasan, F. Awwad, “Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification”, Journal of Electronics Testing Theory and Applications (JETTA), Vol. 32, No. 5, October 2016, pp. 569-86 https://doi.org/10.1007/s10836-016-5619-8
  18. S. F. Mossa,S. R. Hasan, O. S. A. Elkeelany, “Grouped TSV for Lower Ldi/dt drop in 3-D IC”, IET Circuits, Devices and Systems, January 2016 https://doi.org/10.1049/iet-cds.2015.0065
  19. S. R. Hasan, W.Gul, O. Hasan, ” Clock Domain Crossing (CDC) in 3D-SICs: Semi QDI Asynchronous vs Loosely Synchronous”, Integration, the VLSI journal, January 2016 https://doi.org/10.1016/j.vlsi.2015.05.002
  20. G. B. Hamad, S. R. Hasan, O. A. Mohamed, Y. Savaria, “Characterizing, modeling and analyzing soft-error propagation in asynchronous and synchronous digital circuits”, Elsevier’s Microelectronics Reliability 55, no. 1, 2015, pp. 238-250  https://doi.org/10.1016/j.microrel.2014.09.025
  21. G. B. Hamad, S. R. Hasan, O. A. Mohamed, Y. Savaria, “New Insights Into the Single Event Transient Propagation Through Static and TSPC Logic“, IEEE Transaction on Nuclear Science, Vol. 61, No. 4, August 2014, pp. 1618 – 1627 – DOI: 10.1109/TNS.2014.2305434
  22. F.  K. Lodhi, S. R. Hasan, N. Sharif, N. Ramzan and O. Hasan, “Timing Variation Aware Dynamic Digital Phase Detector for Low Latency Clock Domain Crossing”, IET Circuits, Devices & Systems,  Jan, 2014, pp. 58 – 64  DOI: 10.1049/iet-cds.2013.0067
  23. C. Thibeault, Y. Hariri, S.R. Hasan, Y. Savaria, Y. Audet, and F.Z. Tazi, “A Library-Based Early Soft Error Rate Estimation Technique for SRAM-based FPGA Design”, Springer’s Journal of Electronics Testing Theory and Applications (JETTA), Vol. 29., No. 4, August, 2013, pp.  457 – 471 DOI: 10.1007/s10836-013-5393-9
  24. S. R. Hasan, N. Belanger, Y. Savaria, M. O. Ahmad, “All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs”, Elsevier’s Integration, the VLSI journal, Vol. 44, No. 1, January, 2011, pp. 22 – 38 https://doi.org/10.1016/j.vlsi.2010.05.003
  25. S. R. Hasan, N. Belanger, Y. Savaria, M. O. Ahmad, “Crosstalk glitch gating: a solution for designing glitch tolerant asynchronous handshake scheme for GALS systems”, IEEE Transaction on Circuits and Systems Part I (TCAS-I), Vol. 57, No. 10, October 2010, pp. 2696 – 2707  – https://doi.org/10.1109/TCSI.2010.2046981
  26. S. R. Hasan, N. Belanger, Y. Savaria, M. O. Ahmad, “Crosstalk glitch propagation modeling for asynchronous interfaces in globally asynchronous locally synchronous systems”, IEEE Transaction on Circuits and Systems Part I (TCAS-I), Vol. 57, No. 8, August 2010, pp. 2020 – 2031 DOI: 10.1109/TCSI.2009.2038553

Listing of my Peer Reviewed Conference Papers:

  1. A. Adeyemo and S. R. Hasan, “Enhancing the Security of Collaborative Deep Neural Networks: An Examination of the Effect of Low Pass Filters”, accepted for publication in IEEE/ACM Great Lake Symposium on VLSI, June 2023
  2. A. Hakiri, A. S. Gokhale, Y. Barve, V. Formicola, S. Shekhar, C. Mahmoudi, M. A. Rahman, U. Ghosh, S. R. Hasan, T. Guo “Techniques for Realizing Secure, Resilient and Differentiated 5G Operations,” 2022 14th IFIP Wireless and Mobile Networking Conference (WMNC), Sousse, Tunisia, 2022, pp. 113-117, doi: 10.23919/WMNC56391.2022.9954310.
  3. T. Odetola, F. Khalid, S. R. Hasan, “LaBaNI: Layer-based Noise Injection Attack on Convolutional Neural Networks”, in IEEE/ACM Great Lake Symposium on VLSI, June 2022.
  4. J. Nelson, S. R. Hasan, “Compressed Sparse Kernel: Optimization of Pruning for Customized CNNs on FPGAs”, in IEEE International MidWest Symposium on Circuits and Systems, August 2022.
  5. T. Odetola, A. Adeyemo and S. R. Hasan, “Hardening Hardware Accelerator Based CNN Inference Phase against Adversarial Noises”, in Work in Progress session of IEEE International Symposium of Hardware Oriented Security and Trust (HOST), June, 2022.
  6. T. N. Guo, H. Mohammed, S. R. Hasan,  “Edge Intelligence in Mobile Nodes: Opportunistic Pipeline via 5G D2D for On-site Sensing”, in IEEE Vehicular Technology Conference 2022 Workshop on Edge-based AI Applications over B5G/6G Evolution, June 2022.
  7. G. Cataloni, P. Sawyer, S. R. Hasan, “A Primer on Hardware Trojans Including Platform Specific Attacks and Machine Learning for Detection”, in IEEE SouthEast Conference, March, 2022.
  8. A. Adeyemo, T. A. Odetola, S. R. Hasan “Towards Enabling Dynamic Convolution Neural Network Inference for Edge Intelligence”, in IEEE International Symposium on Circuits and Systems–ISCAS’22.
  9. T. Sandefur, S. R. Hasan “Framework to Benchmark CNNs (FaBCNN) for Processing Real-Time HD Video Streams on FPGAs”, in IEEE International Symposium on Circuits and Systems–ISCAS’22.
  10. S. Iqbal, O. Hasan, S. R. Hasan, “Formal Verification of Fault Isolation and Restoration Algorithms in Smart Grid” in 3rd IEEE International Conference on Clean and Green Energy Engineering, August 2022
  11. H. Mohammed, F. Khalid, P. Sawyer, G. Cataloni and S. R. Hasan, “InTrust-IoT: Intelligent Ecosystem based on Golden Dataset Free Power Profiling of Trusted device(s) in IoT for Hardware Trojan Detection”, in Workshop on Hardware and Architectural Support for Security and Privacy (HASP), October, 2021.
  12. T. A. Odetola, S. R. Hasan, “SoWaF: Shuffling of Weights and Feature Maps: A Novel Hardware Intrinsic Attack (HIA) on Convolutional Neural Network (CNN)”, in IEEE International Symposium on Circuits and Systems–ISCAS’21.
  13. H.  Mohammed, T. A.  Odetola, N.  Guo, S. R.  Hasan,  “Dynamic Distribution of Edge Intelligence at the Node Level for Internet of Things”, in 64th IEEE International MidWest Symposium on Circuits and Systems, 2021
  14. J. Nelson, T. A. Odetola, S. R. Hasan, “WORDA: a Winograd Offline-Runtime Decomposition Algorithm for Faster CNN Inference”, in 64th IEEE International MidWest Symposium on Circuits and Systems, 2021.
  15. A. Adeyemo, F. Khalid, T. A. Odetola, S. R. Hasan “Security Analysis of Capsule Network Inference Using Horizontal Collaboration”, in 64th IEEE International MidWest Symposium on Circuits and Systems, 2021.
  16. O Oderhohwo, H Mohammed, T. A. Odetola, T. Guo, S. R. Hasan, F. Dogbe, “An Edge Intelligence Framework for Resource Constrained Community Area Network”, in 63rd IEEE International MidWest Symposium on Circuits and Systems, 2020 (pp. 97 – 100).
  17. O Oderhohwo, H Mohammed, T. A. Odetola, S. R. Hasan, ” Deployment of Object Detection Enhanced with Multi-label Multi-Classification on Edge Devices”, in 63rd IEEE International MidWest Symposium on Circuits and Systems, 2020 (pp. 986 – 989).
  18. H. Mohammed, T. A. Odetola, S. R. Hasan, S. Stissi, I. Garlinx, F. Awwad, “(HIADIoT): Hardware Intrinsic Attack Detection in Internet of Things; Leveraging Power Profiling”, in 62nd IEEE International MidWest Symposium on Circuits and Systems, 2019.
  19. M. Hailesellasie, J. Nelson, F. Khalid, S. R. Hasan, “VAWS: Vulnerability Analysis of Neural Networks using Weight Sensitivity”, in 62nd IEEE International MidWest Symposium on Circuits and Systems, 2019.
  20. M. Bima, I. Bhattacharya, S. R. Hasan, “Comparative Analysis of Magnetic Materials, Coil Structures and Shielding Materials for Efficient Wireless Power Transfer”, in IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity, 2019.
  21. M. T. Hailesellasie, S. R. Hasan, O. A. Mohamed, “MulMapper: Towards an Automated FPGA-Based CNN Processor Generator Based on a Dynamic Design Space Exploration”, in International Symposium on Circuits and Systems (ISCAS, 2019).
  22. J. Zoodsma, J. Dean, S. Spry, J. Dickinson, S. R. Hasan, N. Guo, ” An Intelligent and Secure Cloud Controlled Robotic Arm with Sensor Feedback Feature”, publication in IEEE SouthEast Conference, 2019
  23. A. Pasha, H. Ibrahim, S. R. Hasan, R. Belkacemi, F. Awwad, and O. Hasan, “A Utility Maximized Demand-Side Management for Autonomous Microgrid”, IEEE Electric Power and Energy Conference (EPEC-2018)
  24. S. R. Hasan, Charles Kamhoua, Kevin Kwiat and Laurent Njilla, “A Novel Framework to Introduce Hardware Trojan Monitors Using Model Checking Based Counterexamples: Inspired by Game Theory” in IEEE International MidWest Symposium on Circuits and Systems, 2018
  25. H. Mohammed, J. Howell, S. R. Hasan, N. Guo, O. Elkeelany, ” Hardware Trojan Based Security Issues in Home Area Network:  A Testbed Setup”, in IEEE International MidWest Symposium on Circuits and Systems, 2018
  26. E. Oriero, S. R. Hasan, “All Digital Low Power Aging Sensor for Counterfeit Detection in Integrated Circuits”, in IEEE International MidWest Symposium on Circuits and Systems, 2018
  27. J. Shelley, H. Mohammed, L. Zink, S. R. Hasan, O. Elkeelany, “Covert Communication Channel Detection in Low-Power Battery Operated IoT Devices: Leveraging Power Profiles”, in IEEE SouthEast  Conference,  2018
  28. M. T. Hailesellasie, S. R. Hasan, F. Khalid, M. Shafique, “FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements”, in International Symposium on Circuits and Systems, ISCAS’2018
  29. F. Khalid, S. R. Hasan, S. Nanjiani, O. Hasan, M. Shafique, “Low Power Digital Clock Multipliers for Battery Operated Internet of Things (IoT) Devices”, in International Symposium on Circuits and Systems, ISCAS’2018
  30. A. Y. Salik, M. U. Sardar, O. Hasan, S. R. Hasan, and F. Awwad, “Formal Verification of Demand Response Based Home Energy Management Systems in Smart Grids”, in Innovative Smart-Grid Technologies – Asia, 2017
  31. O. Adegbite, S. R. Hasan, “A Novel Correlation Power Analysis Attack on PIC Based AES-128 without Access to Crypto-Device”, in IEEE International MidWest Symposium on Circuits and Systems, 2017
  32. F. K. Lodhi, S. R. Hasan, O. Hasan, F. Awwad, ” Behavior Profiling of Power Distribution Networks for Runtime Hardware Trojan Detection”, in IEEE International MidWest Symposium on Circuits and Systems, 2017
  33. S. R. Hasan, P. B. Tangellapalli, “Area Efficient Soft Error Tolerant RISC Pipeline: Leveraging Data Encoding and Inherent ALU Redundancy”, in IEEE International MidWest Symposium on Circuits and Systems, 2017
  34. M. T. Hailesellasie, S. R. Hasan, “A Fast FPGA-Based Deep Convolutional Neural Network Using Pseudo Parallel Memories”, in IEEE International Symposium on Circuits and Systems, 2017
  35. K. T. Tanweer, S. R. Hasan, A. M. Kamboh, “Motion Artifact Reduction from PPG Signals During Intense Exercise Using Filtered X-LMS”, in IEEE International Symposium on Circuits and Systems, 2017
  36. S. Kottler, M. Khayamy, S. R. Hasan, O. Elkeelany, “Formal Verification of Ladder Logic programs using NuSMV”, in IEEE SouthEast  Conference,  2017
  37. F. K. Lodhi, S. R. Hasan, O. Hasan, F. Awwad, “Power Profiling of Microcontroller’s Instruction Set for Runtime Hardware Trojans Detection without Golden Circuit Models”, in IEEE/ACM Conference on Design Automation and Test Europe (DATE), Lausanne, Switzerland, 2017
  38. S. R. Hasan, Charles Kamhoua, Kevin Kwiat and Laurent Njilla, “Translating Circuit Behavior Manifestations of Hardware Trojans using Model Checkers into Run-time Trojan Detection Monitors”  in IEEE Asian Hardware Oriented Security and Trust Symposium (AisanHOST), Taipei, Taiwan,  2016
  39. A. Mahmood, O. Hasan, H. R. Gillani, Y. Saleem, and S. R. Hasan, “Formal Reliability Analysis of Protective Systems in Smart Grids”, in IEEE Region 10 Symposium (TENSYMP), Bali, Indonesia, 2016
  40. W. Gul, S. R. Hasan, O. Hasan, F. K. Lodhi, F. Awwad, “Synchronously Triggered GALS Design Templates Leveraging QDI Asynchronous Interface”, in IEEE international symposium of circuits and systems (ISCAS’ 2016
  41. F. K. Lodhi, I. Abbasi , F. Khalid , O. Hasan, F. Awwad and S. R. Hasan, “A Self-learning Framework to Detect the Intruded Integrated Circuit”, in IEEE international symposium of circuits and systems (ISCAS’ 2016)
  42. F. K. Lodhi, S. R. Hasan, O. Hasan, F. Awwad, “Formal Analysis of Macro Synchronous Micro Asynchronous Pipeline for Hardware Trojan Detection”, in IEEE Nordic Circuits and Systems Conference (NORCAS’2015)
  43. S. R. Hasan, S. F. Mossa, O. S. A. Elkeelany, F. Awwad, “Tenacious Hardware Trojans Due to High Temperature in Middle Tiers of 3-D ICs”, in MidWest Symposium on Circuit and Systems (MWSCAS’2015), August, 2015
  44. S. R. Hasan, S. F. Mossa, C. Junior, F. Awwad, “Hardware Trojans in Asynchronous FIFO-Buffers: From Clock Domain Crossing Perspective”, in MidWest Symposium on Circuit and Systems (MWSCAS’2015), August, 2015
  45. F. K. Lodhi, S. R. Hasan, O. Hasan, F. Awwad, “Hardware Trojan Detection in Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline”, in MidWest Symposium on Circuits and Systems (MWSCAS’2014), August, 2014
  46. W. Gul, S. R. Hasan, O. Hasan, “Yield Aware Inter-Logic-Layer Communication in 3-D ICs: Early Design Stage Recommendations”, in MidWest Symposium on Circuits and Systems (MWSCAS’2014), August, 2014
  47. G. B. Hamad, S. R. Hasan, O. A. Mohamed, Y. Savaria, “Modeling, Analyzing, and Abstracting Single Event Transient Propagation at Gate Level”, in MidWest Symposium on Circuits and Systems (MWSCAS’2014), August, 2014
  48. F. K. Lodhi, S. R. Hasan, O. Hasan, F. Awwad, “Low Power Soft Error Tolerant Macro Synchronous and Micro Asynchronous Pipeline”, in IEEE International symposium on VLSI (ISVLSI’ 2014), July 2014
  49. S. F. Mossa, S. R. Hasan, O. S. A. Elkeelany, “Introducing Redundant TSV with Low Inductance for 3-D IC “, in IEEE NEW Circuits and Systems Conference (NEWCAS’ 2014), June 2014
  50. W. Gul, S. R. Hasan, O. Hasan, “Clock Domain Crossing (CDC) for Inter-Logic-Layer Communication in 3-D ICs”, in IEEE NEW Circuits and Systems Conference (NEWCAS’ 2014), June 2014
  51. G. B. Hamad, S. R. Hasan, O. A. Mohamed, Y. Savaria, “Abstracting Single Event Transient Characteristics Variations Due to Input Patterns and Fan out”, in IEEE International Symposium of Circuit and Systems (ISCAS’ 2014)
  52. G. B. Hamad, S. R. Hasan, O. A. Mohamed, Y. Savaria, “Investigating the Impact of Input Patterns, Propagation Paths, and Re-convergent Paths on The Propagation Induced Pulse Broadening”, 2013 IEEE Conference on Radiation Effects on Components and Systems (RADECS’ 2013)
  53. P. B. Tangellapalli, S. R. Hasan, “Soft Error Aware Pipelined Architecture: Leveraging Automatic Repeat Request Protocol”, in 56th IEEE Mid-West Symposium on Circuits and Systems, MWSCAS’2013
  54. Z. Al-Bayati, O. A. Mohamed, S. R. Hasan and Y. Savaria, “Design of a C-Element Based Clock Domain Crossing Interface”, in 24th IEEE/ACM International Conference on Microelectronics (ICM 2012)
  55. P. B. Tangellapalli, S. R. Hasan, “Towards Low Area Overhead ARQ Based Soft Error Tolerant Data Paths for SRAM-Based Altera FPGAs”, in 55th IEEE Mid-West Symposium on Circuits and Systems, MWSCAS’2012
  56. F. K. Lodhi, S. R. Hasan, O. Hasan, F. Awwad, “Modified Null Convention Logic Pipeline to Detect Soft Errors in Both Null and Data Phase”, in55th IEEE Mid-West Symposium on Circuits and Systems, MWSCAS’2012
  57.  G. B. Hamad, O. A. Mohamed, S. R. Hasan, Y. Savaria, “ Identification of Soft-Error Glitch-Propagation Paths: Leveraging SAT solvers,” in IEEE International Symposium for Circuits and Systems, ISCAS’2012
  58.  Z. Al-bayati, S. R. Hasan, O. A. Mohamed, Y. Savaria, “A Novel Hybrid FIFO Asynchronous Clock Domain Crossing Interfacing Method,” in 22nd Edition of ACM/IEEE Great Lake Symposium on VLSI, GLSVLSI’2012
  59. G. B. Hamad, O. A. Mohamed, S. R. Hasan, Y. Savaria, “SEGP-Finder: Tool for Identification of Soft Error Glitch-Propagating Paths at Gate Level”, in 18th IEEE International Conference on Electronics Circuits and Systems, December, 2011
  60. N. Sharif, N. Ramzan, F. K. Lodhi, O. Hasan, and S. R. Hasan, “Quantitative Analysis of State-of-the-Art Synchronizers: Clock Domain Crossing Perspective”, in IEEE International Conference on Emerging Technologies, September 2011
  61. S. R. Hasan, B. Pontikakis, Y. Savaria, “An all-digital skew-adaptive clock scheduling algorithm for multiprocessor systems on chips (MPSoCs)”, in International Symposium on Circuits and Systems (ISCAS 2009), Taipei, Taiwan, May 2009, pp. 2501 – 2504
  62. S. R. Hasan, N. Belanger, Y. Savaria, “All-digital skew-tolerant interfacing method for systems with rational frequency ratios among Multiple Clock Domains: leveraging a priori timing information”, in 1st Microsystems and Nano electronics Research Conference (MNRC 2008) Ottawa, Canada, October 2008, pp. 129 – 132
  63. S. R. Hasan, Y. Savaria, “Metastability tolerant mesochronous synchronization”, in 50th MidWest Symposium on Circuits & Systems, (MWSCAS 2007), Montreal, Canada, August 2007, pp. 13 – 16
  64. S. R. Hasan, Yvon Savaria, “Crosstalk effects in event-driven self-timed circuits designed with 90nm CMOS technology”, in International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, USA, May 2007, pp. 629 – 632
  65. S. R. Hasan, Y. Savaria, M. Nekili, “Split H-tree design method for high-performance GALS systems”, in 4th Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Canada, June, 2006, pp. 161 – 164
  66. S. R. Hasan, A. Landry, Y. Savaria, M. Nekili, “Design constraints of a HyperTransport-compatible network-on-chip”, in 2nd Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montreal, Canada, June, 2004, pp. 269 – 272
  67. A. Upadhyay, S. R. Hasan, M. Nekili, “Optimal partitioning of globally asynchronous locally synchronous processor array”, in the 2004 Great Lakes Symposium on VLSI (GLSVLSI 2004), Boston, USA, April 2004, pp. 7 – 12
  68. A. Upadhyay, S. R. Hasan, M. Nekili, “A novel asynchronous wrapper using1-0f-4 data encoding and single-track handshaking”, in 2nd Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montreal, Canada, June, 2004, pp. 205 – 208

Selected Presentations:

  1. Poster presented by S. R. Hasan to elaborate on the research paper with his PhD students, paper is titled as “LaBaNI: Layer-based Noise Injection Attack on Convolutional Neural Networks”, published in IEEE/ACM Great Lake Symposium on VLSI, June 2022.
  2. Poster presented by S. R. Hasan to elaborate on the research paper with my students. The details of the paper are as follows, title – “VAWS: Vulnerability Analysis of Neural Networks using Weight Sensitivity”, published in 62nd IEEE International MidWest Symposium on Circuits and Systems, 2019, by M. Hailesellasie, J. Nelson, F. Khalid, S. R. Hasan
  3. Lecture presented by S. R. Hasan on the paper titled as “A Novel Framework to Introduce Hardware Trojan Monitors Using Model Checking Based Counterexamples: Inspired by Game Theory”, by S. R. Hasan, Charles Kamhoua, Kevin Kwiat and Laurent Njilla. in IEEE International MidWest Symposium on Circuits and Systems, 2018
  4. Lecture presented by S. R. Hasan, “All Digital Low Power Aging Sensor for Counterfeit Detection in Integrated Circuits”, having authors E. Oriero, and S. R. Hasan, in IEEE International MidWest Symposium on Circuits and Systems, 2018
  5. Lecture presented by S. R. Hasan to elaborate on the research paper, “A Novel Correlation Power Analysis Attack on PIC Based AES-128 without Access to Crypto-Device”, by O. Adegbite, S. R. Hasan, in IEEE International MidWest Symposium on Circuits and Systems, Boston, MA, 2017.
  6. Lecture presented by S. R. Hasan to elaborate on the research paper, ” Behavior Profiling of Power Distribution Networks for Runtime Hardware Trojan Detection”, by F. K. Lodhi, S. R. Hasan, O. Hasan, F. Awwad, in IEEE International MidWest Symposium on Circuits and Systems, Boston, MA, 2017
  7. Lecture presented by S. R. Hasan on “Towards Run-Time Hardware Trojan Detection Using Circuit Behavior Profiling: Leveraging Game Theory and Formal Verification”, in 3rd annual colloquium  on Game Theory at Air Force Research Lab (AFRL), Rome, NY – July 2016
  8. Invited lecture by S. R. Hasan on “Digital Hardware Design Security”, at National University of Science and Technology (NUST), Islamabad, Pakistan – May 2016
  9. Invited lecture by S. R. Hasan on “Towards Run-Time Hardware Trojan Detection Using Circuit Behavior Profiling: Leveraging Formal Verification”, at Florida Polytechnic University, Lakeland, FL – January 2016
  10. Poster presented by S. R. Hasan on “Tenacious Hardware Trojans Due to High Temperature in Middle Tiers of 3-D ICs”, an extended abstract in Design Automation Conference (DAC), 2015 (The co-authors are S. F. Mossa, O. S. A. Elkeelany)
  11. Lecture presented by S. R. Hasan to elaborate on the research paper, “Hardware Trojan Detection in Soft Error Tolerant Macro Synchronous Micro Asynchronous (MSMA) Pipeline”, by F. K. Lodhi, S. R. Hasan, O. Hasan, F. Awwad, in MidWest Symposium on Circuits and Systems (MWSCAS’2014), August, 2014
  12. Lecture presented by S. R. Hasan to elaborate on the research paper, “Modeling, Analyzing, and Abstracting Single Event Transient Propagation at Gate Level”, by G. B. Hamad, S. R. Hasan, O. A. Mohamed, Y. Savaria, in MidWest Symposium on Circuits and Systems (MWSCAS’2014),  August, 2014
  13. Poster presented by S. R. Hasan to elaborate on the research paper, “Yield Aware Inter-Logic-Layer Communication in 3-D ICs: Early Design Stage Recommendations”, by W. Gul, S. R. Hasan, O. Hasan, in MidWest Symposium on Circuits and Systems (MWSCAS’2014), August, 2014
  14. Lecture presented by S. R. Hasan to elaborate on the research paper, “Low Power Soft Error Tolerant Macro Synchronous and Micro Asynchronous Pipeline”, by F. K. Lodhi, S. R. Hasan, O. Hasan, F. Awwad, in IEEE International symposium on VLSI (ISVLSI’ 2014), July 2014
  15. Lecture presented by S. R. Hasan to elaborate on the research paper, “Clock Domain Crossing (CDC) for Inter-Logic-Layer Communication in 3-D ICs”, by W. Gul, S. R. Hasan, O. Hasan, in IEEE NEW Circuits and Systems Conference (NEWCAS’ 2014), June 2014
  16. Poster presented by S. R. Hasan to elaborate on the research paper, “Introducing Redundant TSV with Low Inductance for 3-D IC “, by S. F. Mossa, S. R. Hasan, O. S. A. Elkeelany,in IEEE NEW Circuits and Systems Conference (NEWCAS’ 2014), June 2014
  17. Lecture presented by S. R. Hasan to elaborate on the research paper “Soft Error Aware Pipelined Architecture: Leveraging Automatic Repeat Request Protocol”, by P. B. Tangellapalli and S. R. Hasan, in 56th IEEE Mid-West Symposium on Circuits and Systems, MWSCAS’2013, Columbus, OH
  18. Poster presented by S. R. Hasan to elaborate on the research paper, “Towards Low Area Overhead ARQ Based Soft Error Tolerant Data Paths for SRAM-Based Altera FPGAs”, by P. B. Tangellapalli and S. R. Hasan, in 55th IEEE Mid-West Symposium on Circuits and Systems, MWSCAS’2012
  19. Poster presented by S. R. Hasan to elaborate on the research paper, “Modified Null Convention Logic Pipeline to Detect Soft Errors in Both Null and Data Phase”, by F. K. Lodhi et. al. in 55th MWSCAS’2012, Boise, Idaho
  20. Poster presented by S. R. Hasan to elaborate on the research paper, “A Novel Hybrid FIFO Asynchronous Clock Domain Crossing Interfacing Method”, by Z. Al-bayati, S. R. Hasan, O. A. Mohamed, and Y. Savaria, in 22nd Edition of ACM/IEEE Great Lake Symposium on VLSI, GLSVLSI’2012, Salt Lake City, Utah
  21. A presentation by S. R. Hasan on “Towards Soft Error Rate Estimation in SRAM-Based FPGA Designs”, during the kick-off meeting for the project of Cosmic Radiation and effect on aircraft system: a research project conducted by Consortium for Research and Innovation in Aerospace in Quebec, February 2011, Montreal, QC
  22. A presentation by S. R. Hasan on “Radiation Induced Single Event Effects in Modern Avionics”, to provide awareness about growing radiation hazards to commercial airplane industry, October 2009, Montreal, QC
  23. Poster presented by S. R. Hasan to elaborate on the abstract, “Understanding the radiation hazards in integrated circuits at airplane flying altitudes”, by S. R. Hasan, N. Bélanger, Y. Audet, Y. Savaria, C. Thibeault, in CANEUS Fly-By-Wireless Workshop 2009,  (FBW 2009), June 2009, Montreal, QC, Canada
  24. A presentation by S. R. Hasan on “Introduction to Radiation Hazards in Integrated Circuits and Modeling Approaches”, in a meeting of a joint project among aero-space industry and academia, March 2009, Montreal, Canada
  25. Poster presented by S. R. Hasan to elaborate on the research paper “All-digital skew-tolerant interfacing method for systems with rational frequency ratios among multiple clock domains: leveraging a priori timing information”, by S. R. Hasan, N. Belanger, Y. Savaria, in Microsystems and Nano electronics Research Conference (MNRC 2008), Canada.
  26. Lecture presented by S. R. Hasan to elaborate on the research paper “Metastability tolerant mesochronous synchronization”, by S. R. Hasan, Y. Savaria, in 50th MWSCAS 2007, Montreal, Canada, August 2007
  27. Lecture presented by S. R. Hasan on “A H-tree Splitting Method for High-Performance GALS-Based SoCs”, during a seminar conducted by ECE Department, Concordia University, Montreal, Canada, November, 2005
  28. Poster presented by S. R. Hasan to elaborate on the research paper “Split H-tree design method for high-Performance GALS Systems”, by S. R. Hasan, Y. Savaria, M. Nekili, in 4th Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Canada, June, 2006
  29. Lecture presented by S. R. Hasan to elaborate on the research paper “Design constraints of a HyperTransport-compatible network-on-chip”, by S. R. Hasan, A. Landry, Y. Savaria, M. Nekili, in 2nd NEWCAS 2004, Canada
  30. Poster presented by S. R. Hasan to elaborate on the research paper “A novel asynchronous wrapper using1-of-4 data encoding and single-track handshaking”, by Upadhyay, S. R. Hasan, M. Nekili, in 2nd NEWCAS 2004, Canada